1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, such as a flash memory, of which charge injection is a source side injection (hereafter called “SSI”) and the charge storage format is MONOS (Metal-Oxide-Nitride-Oxide Semiconductor). The present invention also relates to a drive method of such non-volatile semiconductor memory device, and a manufacturing method of such non-volatile semiconductor memory device.
2. Description of the Related Art
The conventional technology on a non-volatile semiconductor memory drive, such as a flash memory, is disclosed, for example, in Japanese Patent Laid-Open No. 2001-168219 and Japanese Patent Laid-Open No. 2003-51558.
Japanese Patent Laid-Open No. 2001-168219 discloses a non-volatile semiconductor memory, such as a flash memory, which can improve the write speed while maintaining the operation voltage to a constant voltage.
As Japanese Patent Laid-Open No. 2001-168219 discloses, a non-volatile semiconductor memory has an FG (Floating Gate) type, in which the storage means for holding charges is continuous on a plane, and a MONOS type, in which the charge storage means is discrete on a plane. In the MONOS type, a carrier trap is spatially spread (in the plane direction and film thickness direction) in a nitride film which primarily holds charges, or in the interface of the top insulation film and nitride film. Thus, the charge holding characteristics depends on the energetic and spatial distribution of the charges trapped in the tunnel insulation film and in the carrier trap of the nitride film. In the case of the FG type, if a leak current path is locally generated in this tunnel insulation film, many charges pass through the leak path, and the charge holding characteristics drop. On the other hand, in the case of the MONOS type, the charge storage means is spatially discrete, so that only some charges around the leak path leak locally. Thus, the charge holding characteristics do not drop very much, and the MONOS type is superior to the FG type in miniaturizing the memory cells by decreasing the gate length. In order to implement a micro-memory by the MONOS type, an improvement of the disturb characteristic (write error characteristic) is critical. To achieve this improvement, it is necessary to increase the film thickness of the tunnel insulation film. However, the increased film thickness makes it difficult to improve the write speed with a low operation voltage.
In order to increase the write speed while reducing an operation voltage, Japanese Patent Laid-Open No. 2001-168219 proposes an improved MONOS type non-volatile semiconductor memory device. This non-volatile semiconductor memory device includes a substrate, a channel formation region on the surface of the substrate, a source region and drain region formed on the surface of the substrate sandwiching the channel formation region, a gate insulation film which encloses the charge storage means (carrier trap) which is discrete in the plane direction facing the channel formation region and in the film thickness direction, and a gate electrode formed on the gate insulation film.
The non-volatile semiconductor memory according to Japanese Patent Laid-Open No. 2001-168219 can smoothly store 1 bit of data in one memory cell, but when storing two bits of data, complicated control is required on the operation voltage to be applied. Japanese Patent Laid-Open No. 2003-51558 proposes a technology to overcome this problem.
In Japanese Patent Laid-Open No. 2003-51558, the MONOS type non-volatile semiconductor memory device injects charges for writing from the substrate side into the gate insulation film having the charge storage means. For erasing, the stored charges are drained to the substrate side, or charges with reverse polarity, to cancel the stored charges, are injected into the gate insulation film. To inject charges, the tunnel phenomena of charges in the gate insulation film is used, or charges are energetically excited up to a level which allows them to mount (climb) the insulation barrier of the lowest layer of the gate insulation film (CHE (Channel-Hot-Electron) injection). The SSI method is known as a type of CHE.
In the SSI method, an electrode for controlling the drain side channel and an electrode for controlling the source side channel are formed separately. When charges are injected, the drain side channel is set to a strong inversion status and the source side channel is set to a weak inversion status. As a result, a high electric field is generated around the boundary of the drain side channel and source side channel, and charges supplied from the source side are excited by this high electric field. The charges are then supplied from the source side to the charge storage means under the electrode for controlling the drain side channel. This injection efficiency is improved by about one digit compared with an ordinary CHE injection.
In order to further improve the injection efficiency of the SSI method, the MONOS type non-volatile semiconductor memory device based on the SSI method according to Japanese Patent Laid-Open No. 2003-51558 includes: a second conductive type inversion layer formation region which is formed in a channel formation region on the surface of the substrate such that a channel is formed by an inversion layer; a first conductive type first and second storage layer formation regions which are disposed on both sides of the inversion layer formation region in the channel formation region such that a channel is formed by a multi-carrier storage layer, a first conductive type source region and drain region formed outside the first and second storage layer formation regions; a first memory gate electrode formed on the first storage layer formation region and the source region via a first multi-layer film which has a charge storage capability; a second memory gate electrode formed on the second storage layer formation region and the drain region via the second multi-layer film which has a charge storage capability; and a control gate electrode formed on the inversion layer formation region via a single layer dielectric film which has no charge storage capability.
The operation, when electrons are injected into the second multi-layer film by the SSI method, is described. In writing, the reference voltage Vs (=0V) is applied to the source region, drain voltage Vd (=5.0V) to the drain region, positive voltage Vcg (=1.0V) to the control gate electrode, and positive voltage Vmg (=7.0V) to the first and second memory gate electrodes. As a result, the inversion layer is formed in the inversion layer formation region, and the storage layers are formed on the first and second storage layer formation regions on both sides of the inversion layer. Electrons supplied from the storage layer at the source side are accelerated in the inversion layer, and a part of the electrons becomes Hot-Electrons which mount over the energy barrier in the second multi-layer film at the drain side, and a part of these high energy electrons is injected into the second multi-layer film at a certain probability.
The potential difference between the drain voltage Vd and the source voltage Vs is mainly applied to the channel region directly under the space between the control electrode and second memory gate electrode at the drain side, and a high electric field is generated in this channel region. Because this high electric field makes electrons in the inversion layer channel into high energy electrons, electrons are injected into the second multi-layer film. In order to increase this injection efficiency, the voltage to be applied to the control gate electrode and second memory gate electrode is controlled so that the electric field in the channel direction concentrates to the same region as the electric field in the vertical direction of the channel concentrates.
When writing is performed to the first multi-layer film at the source side, electrons are efficiently injected into the first multi-layer film by reversing the voltage relationship between the source region and drain region based on the same principle. Consequently, 2-bit data can be independently written to one memory cell.
In the MONOS type non-volatile semiconductor memory device based on SSI disclosed in Japanese Patent Laid-Open No. 2003-51558, the charge injection efficiency is high and high-speed operation is possible, but the memory structure is complicated and manufacturing is very difficult, since three gate electrodes (first and second memory gate electrodes and control gate electrode) are formed in one memory cell, and the first and second storage layer formation regions are formed on both sides of the inversion layer formation region in the channel formation region. Also, control is complicated because the number of voltages to be applied to the gate electrodes and other components during operation is numerous.